As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Information handling systems employ solid-state storage devices, (e.g., solid-state drives) to store data and programs of instructions for later retrieval. A solid-state drive (SSD) is a data storage device that uses solid-state memory to store persistent data. A SSD may emulate a hard disk drive interface to easily replace a hard disk drive. SSDs often use NAND flash memory as an underlying storage medium. A page is the smallest NAND unit which may be written, and one of the limitations for writing to most NAND flash memory is that a page of memory must be empty before it is written to. Thus, if data exists in the page, the page must be erased before data is written to it. A SSD may track data stored thereon using a Flash Translation Layer (FTL) mapping table that maintains the location in the SSD for each data segment (data block) corresponding to a logical block address (LBA) with which it is written. In Flash memory, a data block is the smallest unit size that may be erased in an SSD. Accordingly, two approaches may typically be used to rewrite data to an SSD. If the new data is smaller than the smallest erase unit size of the SSD (e.g., a FTL block), the existing data is read and merged with the new data, with the merged data written to a new location in the SSD. After data is written to the new location, the old location is invalidated. If the new data is larger than the smallest erase unit size of the SSD, new data is written to a different location of the flash memory and the old location is invalidated.
Over time, the SSD may include many “dirty” blocks that contain invalid data. In order to continue writing to blocks, a controller of the SSD “cleans” these blocks by performing a function known as garbage collection. Garbage collection typically includes the act of determining memory blocks that include a threshold level amount of invalid data. Valid data from such blocks is collected, aggregated, and written to new SSD memory locations, and the old blocks are erased.
Traditional single-level cell (SLC) NAND media stores one bit per cell. However, NAND memory has been scaled up in density by putting more bits in a single cell at the expense of lower media endurance and degraded performance. Examples of denser types of NAND media include what is commonly referred to as multi-level cell (MLC) memory having two bits per cell, triple-level cell (TLC) memory having three bits per cell, and quad-level cell (QLC) memory having four bits per cell. Scaling up the number bits stored per cell introduces degrading performance as well as lower endurance of the media, and the performance and endurance level of current QLC memory devices is only marginally acceptable for current memory applications. Higher performance media has been placed in the data-receiving front of a NAND memory device as an input data buffer for a main section of lower performance media of the NAND memory device. In such a configuration, the SSD controller empties the higher performance media buffer by evicting existing data to the lower performance media. However, in such a configuration the endurance level of the lower performance media may be exceeded during memory device operation, especially where the lower performance media has an endurance level as low as 100 to 300 program & erase cycles, e.g., such as is the case with existing QLC memory.
FIG. 1 is a simplified representation of NAND media of a conventional memory device 100 that includes an input buffer section 102 of higher performance/higher endurance SLC media and a main memory section 104 of lower performance/lower endurance QLC media. As shown in FIG. 1, buffer 102 currently includes multiple memory blocks 110a to 110c that each contain FTL pages of valid (non-hashed) and invalid (hashed) data. In this case, memory block 110a includes three pages of high frequency LBA update data (e.g., LBA data that is updated by writing at a frequency greater or equal to 3 sigma distributed frequency) that have all been invalidated and one page of invalid low frequency LBA update data (e.g., LBA data that is updated for writing at a frequency less than 3 sigma distributed frequency), memory block 110b includes two pages of invalid high frequency update data and two pages of valid low frequency LBA update data, and memory block 110c includes two pages of invalid high frequency LBA update data and two pages of valid high frequency LBA update data. As shown, the two valid (non-hashed) data pages of memory block 110c may contain high frequency LBA update data #1 and #2 that has replaced previously existing high frequency update LBA data #1 and #2 of various other, now invalidated, data pages contained in memory blocks 110a, 110b and 110c as shown. Since high frequency LBA update data is written to the NAND media of memory device 100 more often, buffer 102 may at any time contain more invalidated pages of high frequency LBA update data than pages of invalidated low frequency LBA update data. The conventional memory device 100 does not monitor the relative frequency of LBA update, and is unaware of which data pages contain high frequency LBA update data and low frequency LBA update data.
Still referring to FIG. 1, a garbage collection cycle begins by collecting, aggregating, and writing valid LBA data from pages of the various memory blocks 110a to 110c of input buffer section 102 to new SSD memory locations in main memory section 104. In the illustrated example of FIG. 1, valid low frequency LBA update data #1 and #2 from the two pages of memory block 110b have been aggregated with valid high frequency LBA update data #1 and #2 of pages from memory block 110c, and written together to a memory block 112 of main memory section 104. The memory blocks 110a to 110c of buffer section 102 are then erased to allow new incoming LBA data to be written to buffer section 102 as shown in FIG. 2. In this case, new incoming high frequency LBA update data #1 and high frequency LBA update data #2 is subsequently written to two data pages of memory block 110a, which causes invalidation of corresponding existing high frequency LBA update data #1 and #2 of two pages of memory block 112 of main memory section 104 as illustrated by the check marks. Because invalidated high frequency LBA update data pages now reside in memory block 112 of lower performance/lower endurance QLC media main memory section 104, the valid low frequency LBA update data in the remaining two pages of memory block 112 in the lower performance/lower endurance QLC media will be read and rewritten (with other currently valid LBA data pages) to a new data block in main memory section 104 (and memory block 112 erased) during the next garbage collection cycle.